In recent years, in the area of semiconductor memory devices such as DRAM, 4M DRAM has been mass-produced and 16M DRAM has been actively studied. In other words, for 16M DRAM, the submicron stage represented by 4M DRAM is opened and a 3-dimensional device structure is introduced in addition to a reduction in conventional proportions, resulting in extreme fineness of materials.
In DRAM, according to the memory cell structure, the typical three dimensional structures such as a trench type and a stack type have been extensively studied. The trench type is manufactured in such a manner that a capacitor is formed inside the groove provided on the semiconductor substrate, and the stack type is constructed such that a capacitor is formed by laminating in three dimensions the conductive layers on the surface of the semiconductor substrate. Compared with stack type, the trench type has a more flat surface, resulting in advantages for lithography. But the trench type has disadvantages. First, the operation voltage is changed by leakage of current and punch-through between a trench and its neighboring trench. Also, there is the problem of electron-hole pairs generated by .alpha.-particles transmitted inside the substrate. The stack type is formed by laminating element layers on the substrate, so that the fabrication process sequence is simpler than that of trench type, and does not have the disadvantages of the trench type as stated above. As a result, the stack type is more profitable than the trench type.
To attain the required effective capacitance in the limited cell area, the stack type has to utilize the capacitor area maximally. In the conventional stack type, a thin insulating film covers the upper surface and the side surface of the storage electrode layer and then the plate electrode layer is formed on the thin insulating film. Therefore, because of the limited cell area resulting from the decreased cell size necessary to achieve VLSI, to maintain or increase effective capacitance, the height of the staked layers should be higher. This has the disadvantageous result of deteriorating the topography of the overall device.